ACROMAG XMC-VLX85
Description
XMC-VLX: User-Configurable Virtex-5 FPGA Modules with Plug-In I/O
Acromag's XMC-VLX boards feature a reconfigurable Xilinx® Virtex™-5 FPGA enhanced with multiple high-speed memory buffers and a high-throughput PCIe interface. Field I/O interfaces to the FPGA via the rear J4/P4 connector and/or with optional front mezzanine AXM plug-in I/O modules. The result is a powerful and flexible I/O processor module that is capable of executing your custom instruction sets and algorithms. Three models provide a choice of logic-optimized FPGAs to match your performance requirements. Although there is no limit to the uses for these boards, several applications are ideal. Typical uses include hardware simulation, communications, military servers, in-circuit diagnostics, signal intelligence, and image processing. Watch: FPGA Computing for Speed and FlexibilityUser-configurable Virtex-5 FPGA, 85k logic cells
Part Number
XMC-VLX85
Price
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Manufacturer
ACROMAG
Lead Time
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Category
XMC Products » XMC FPGA Boards
Specifications
Categorization Information
Embedded I/O & Processors
XMC Products
XMC FPGA Boards
Virtex-5 Series
Features
- XMC-VLX85: 82,944 logic cells (XC5VLX85T)
- XMC-VLX110: 110,592 logic cells (XC5VLX110T)
- XMC-VLX155: 155,648 logic cells (XC5VLX155T)
- Reconfigurable Xilinx Virtex-5 FPGA
- PCIe bus 4-lane Gen 1 interface
- Supports both front and rear I/O connections
- 64 I/O or 32 LVDS lines direct to FPGA via rear (J4)
- Plug-in I/O modules are available for front mezzanine
- FPGA code loads from PCI bus or flash memory
- Two banks of 1Mb x 32-bit dual-ported SRAM
- Two banks of 32Mb x 16-bit DDR2 SDRAM
- Other memory options available (contact factory)
- Supports dual DMA channel data transfer to CPU/bus
- Support for Xilinx ChipScope™ Pro interface
- Conduction-cooled, 0 to 70°C or -40 to 85°C (E versions)
Datasheet
AXM-A30%20PMC%20Analog%20Input%20Extension%20Modules.pdf
58 KiB
Extracted Text
PMC Modules PMC Modules Block Diagram PCI Bus Connector 16MB FPGA Flash Memory Configuration CPLD 6 8 P Configurable I/O Transceivers i FPGA n PCI Bus • TTL I/O Interface Virtex II C • Differential (RS-422) I/O Controller o n 500K or 2M • TTL/Differential combo PLX9056 n System Gates e • LVDS I/O c t o r DC-to-DC 256K x 36 Power Supply RAM Memory Engineering Design Kit This kit provides you with the basic information required to develop a custom FPGA program for down- load to the Xilinx FPGA. Utilities help you load VHDL into the FPGA, and to establish DMA transfers between the FPGA and the CPU. It is also recommended that users should be familiar with Xilinx development tools. Acromag’s Engineering Design Kit includes: n Parts list and location n Schematics n Compiled FPGA file n Example VHDL code provided as selectable blocks of code Local Bus – example interface between PLX PCI9056 and FPGA SRAM – example code for read and write transfers to SRAM Interrupts – examples of change-of-state monitoring and interrupts to the PCI bus Field I/O – examples of direction control and I/O read/write capability Pin definitions – configuration file containing definition of all user I/O pins communicating with the FPGA Acromag, Inc. • PO Box 437, Wixom, MI 48393 • Phone: 248-295-0310 • Fax: 248-624-9234 • solutions@acromag.com • www.acromag.com 8400- 430d Printed in USA 1/07 Copyright © 2006 Acromag, Inc. Data subject to change without notice All trademarks are the property of their respective owners. PMC Modules
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