AXM-A30 - ACROMAG - IPC Station

Description

AXM-A30: Analog Input
This module features two 105MHz 16-bit A/D channels. An external clock and trigger can be used to control sampling. An internal precision clock conditioner provides the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. Each clock distribution block includes a programmable divider, a phase synchronization circuit, and a programmable delay. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to multiple system components. Watch: FPGA Computing for Speed and FlexibilityAXM plug-in I/O module: Two 16-bit 105MHz A/D channels.

Part Number

AXM-A30

Price

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Manufacturer

ACROMAG

Lead Time

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Category

XMC Products » XMC FPGA Boards

Specifications

Analog Input • Input configuration: Two differential channels using two Analog Devices AD9460 A/D converter.

Input configuration: Two differential channels using two Analog Devices AD9460 A/D converter.
A/D resolution: 16 bits.
Input range: 3.4V peak-to-peak, centered at 0V, into a 50 ohm load.
External clock input: 3.3V peak-to-peak.
Input clock range:1-105MHz.
Maximum throughput rate: 1 channel (max.): 9.5nS (105MHz). 2 channels (max.): 9.5nS (105MHz). A/D trigger: External source, FPGA controlled.
Input clock controller:Precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock.
Signal-to-noise ratio: 69dB (25°C) typical.
Signal-to noise and distortion: 67dB (25°C) typical.
General purpose I/O: Low voltage TTL.

Physical Dimensions

Size: 11.5 mm high x 31.0 mm deep x 74.0 mm wide (0.453 inches x 1.220 inches x 2.913 inches)
Stacking height: 5.0 mm (0.197 inches).
Complies with PMC Specification P1386.1 for a single-width PMC module when installed on a supported PMC module.

Connectors

Front field I/O: Four SMA PCB jack female receptacle connectors.

Categorization Information

Embedded I/O & Processors
XMC Products
XMC FPGA Boards
I/O Extension Modules

Datasheet

AXM-A30%20PMC%20Analog%20Input%20Extension%20Modules.pdf

58 KiB

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Extracted Text

PMC Modules PMC Modules Block Diagram PCI Bus Connector 16MB FPGA Flash Memory Configuration CPLD 6 8 P Configurable I/O Transceivers i FPGA n PCI Bus • TTL I/O Interface Virtex II C • Differential (RS-422) I/O Controller o n 500K or 2M • TTL/Differential combo PLX9056 n System Gates e • LVDS I/O c t o r DC-to-DC 256K x 36 Power Supply RAM Memory Engineering Design Kit This kit provides you with the basic information required to develop a custom FPGA program for down- load to the Xilinx FPGA. Utilities help you load VHDL into the FPGA, and to establish DMA transfers between the FPGA and the CPU. It is also recommended that users should be familiar with Xilinx development tools. Acromag’s Engineering Design Kit includes: n Parts list and location n Schematics n Compiled FPGA file n Example VHDL code provided as selectable blocks of code Local Bus – example interface between PLX PCI9056 and FPGA SRAM – example code for read and write transfers to SRAM Interrupts – examples of change-of-state monitoring and interrupts to the PCI bus Field I/O – examples of direction control and I/O read/write capability Pin definitions – configuration file containing definition of all user I/O pins communicating with the FPGA Acromag, Inc. • PO Box 437, Wixom, MI 48393 • Phone: 248-295-0310 • Fax: 248-624-9234 • solutions@acromag.com • www.acromag.com 8400- 430d Printed in USA 1/07 Copyright © 2006 Acromag, Inc. Data subject to change without notice All trademarks are the property of their respective owners. PMC Modules

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