ACROMAG XMC-6VLX240

XMC Modules XMC-6VLX User-Configurable Virtex-6 FPGA Modules P4 P16 High-Speed SFP Port (optional) X1 X4 X4 11 LVDS Pairs, 17 LVDS Pairs, 2 Global Clock Pairs, 2 Global Clock Pairs USB, GND Dual QDR2 SRAM 36 x 2 72Mb 30 LVDS Pairs, JTAG 2 Global Clock Pairs (2M x 36) Quad XC6VLX240 DDR3 SDRAM or 16 x 4 2Gb P15 XC6VLX365 (128M x 16) 36-Pin X4 / X8 Connector X1 (optional) Parallel Platform Flash Flash 256Mb 128Mb High-Speed (16M x 16) (8M x 16) SFP Port (optional) XMC module with PCIe and SRIO/Aurora interface ◆ Logic-optimized Virtex-6 FPGA ◆ Gigabit Ethernet Models with front I/O add dual SFP ports and Description Key Features & Benefits a VHDCR connector. The two SFP ports each Acromag’s XMC-6VLX modules feature a high- ■ Reconfigurable Xilinx Virtex-6 FPGA with provide a copper or fibre interface of up to ® ® performance user-configurable Xilinx Virtex -6 240k or 365k logic cells 2.5Gbps. They also support a Gigabit Ethernet FPGA enhanced with high-speed memory and a ■ 2M x 72-bit QDRII SRAM, interface. The VHDCR connector interfaces JTAG, high-throughput serial interface. The result is a 128M x 64-bit DDR3 SDRAM USB, and 22 SelectIO. powerful and flexible I/O processor module that is capable of executing custom instruction sets ■ 16M x 16-bit parallel flash memory for With Acromag’s Virtex-6 FPGA modules, you and algorithms. MicroBlaze program code storage can greatly increase DSP algorithm performance for faster throughput using multiple channels The logic-optimized FPGA is well-suited for a ■ 128Mb platform flash memory to store power- and parallel hardware architectures. Free up DSP broad range of applications. Typical uses include up configuration bit file for Virtex-6 FPGA processor CPU cycles by offloading algorithmic- hardware simulation, communications, in-circuit ■ Dual 8-lane high-speed serial interfaces on intensive tasks to the FPGA co-processor. diagnostics, military servers, signal intelligence, rear P15 and P16 connectors for PCIe Gen 1/2, and image processing. These modules are ideal for high-performance Serial RapidI/O, 10Gb Ethernet, Xilinx Aurora customized embedded systems. Optimize Two Versions: Rear I/O or Front + Rear ■ Dual SFP ports for Fibre Channel or GbE your system performance by integrating high- Two versions of this module are available, each speed programmable logic with the flexibility ■ 60 SelectI/O or 30 LVDS pairs plus 2 global offering a choice of an FPGA device with 240k or of software running on MicroBlaze™ soft clock pairs direct to FPGA via rear P4 port 365k logic cells. One version provides only rear processors. I/O for use in air or conduction-cooled systems. ■ 34 SelectI/O or 17 LVDS pairs plus 2 global Acromag’s Engineering Design Kit provides The other version adds two SFP ports and a clock pairs direct to FPGA via rear P16 port software utilities and example VHDL code to 36-pin connector on the front but only supports ■ 22 SelectI/O, 2 global clock pairs, JTAG, USB, simplify your program development and get air-cooled systems. and ground signals via front 36-pin connector you running quickly. A JTAG interface enables On all versions, the rear I/O provides an 8-lane on-board VHDL debugging. Additional Xilinx ■ DMA support provides data transfer between high-speed serial interfaces on both the P15 tools help finish your system faster. Maximize system memory and the on-board memory and P16 XMC ports for PCI Express, Serial ® FPGA performance with ISE Design Suite. And RapidIO, 10-Gigabit Ethernet, or Xilinx Aurora ■ Support for Xilinx ChipScope™ Pro interface with ChipScope™ Pro tools, you can rapidly implementation. P16 also supports 34 SelectIO debug logic and serial interfaces ■ Designed for conduction-cooled host card channels. The P4 port adds another 60 SelectIO and global clock lines. SelectI/O signals are Virtex-6 FPGA I/O pins that support single-ended I/O (LVCMOS, HSTL, SSTL) and differential I/O standards (LVDS, HT, LVPECL, BLVDS, HSTL, SSTL). ■ ■ ■ ■ Tel 248-295-0310 Fax 248-624-9234 solutions@acromag.com www.acromag.com 30765 Wixom Rd, Wixom, MI 48393 USA Bulletin #8400-651e XMC Modules XMC-6VLX User-Configurable Virtex-6 FPGA Modules ■ Electrical Performance Specifications Ordering Information XMC PCIe bus interface (P15 and P16) NOTE: XMC-6VLX-EDK is required to configure FPGA. One 114-pin male connector ■ FPGA (Samtec ASP-103614-05 or equivalent). ■ XMC Modules FPGA device P15 primary XMC connector Xilinx Virtex-6 FPGA. XMC-6VLX240 8 differential pairs (Serial RapidIO, PCIe, 10-Gigabit User-configurable Virtex-6 FPGA, 240k logic cells, Model XC6VLX240T FPGA with 241,152 logic cells Ethernet, or Xilinx Aurora). JTAG. no front I/O and 768 DSP48E1 slices or Model XC6VLX365T with System Management (XMC provides hardware 364,032 logic cells and 576 DSP48E1 slices. XMC-6VLX240F definition information read by an external controller Same as XMC-6VLX240 plus SFP front I/O FPGA configuration using IPMI commands and I2C serial bus transactions.) Download via JTAG or flash memory. XMC-6VLX365 3.3V power: 4 pins at 1A/pin. User-configurable Virtex-6 FPGA, 365k logic cells, Example FPGA program 3.3V auxiliary power: 1 pin for system management. no front I/O VHDL provided for bus interface, front & rear I/O Variable power (5V or 12V): 8 pins at 1A per pin. control, SRAM read/write interface logic, and SDRAM XMC-6VLX365F P16 XMC connector memory interface controller. See EDK kit. Same as XMC-6VLX365 plus SFP front I/O 8 differential pairs (Serial RapidIO, PCIe, 10-Gigabit Ethernet, or Xilinx Aurora). 17 LVDS pairs or 34 SelectI/O signals (differential pairs ■ I/O Processing ■ Accessories grouped per VITA 46.0 X38s). Front high-speed I/O 5025-921 2 global clock pairs. Two x1 lanes via SFP connectors for Gigabit Ethernet Cable, VHDCI 36-pin to SCSI-2, 6 feet long. Use with and Fibre Channel interface Vcco pins are powered by 2.5V and support the 2.5V XMC-6VLX240F and XMC-6VLX365F. I/O standards. Front user I/O 5028-449 36-pin connector provides JTAG connection, USB P4 PMC rear I/O connector Cable, copper twin-ax, SFP to SFP, 1 meter long. signals, 2 global differential clock pairs, 11 LVDS signal 64-pin female receptacle header 5028-455 pairs, and 2 ground signals. (AMP 120527-1 or equivalent). Transceiver, 10/100/1000BASE-T copper SFP, Rear high-speed I/O 64 I/O connections (30 LVDS pairs plus two global up to 1.25Gb/s bi-directional data links. 16 high-speed serial lanes. clocks). 5028-452 x8 lanes via P15 and x8 lanes via P16. Vcco pins powered by 2.5V and support the 2.5V I/O Transceiver, short-wavelength SFP, Rear user I/O standards. up to 2.125Gb/s bi-directional data links. P16: 17 LVDS pairs (34 LVCMOS), 2 global clock pairs. VHDCR connector P4: 30 LVDS pairs (60 LVCMOS), 2 global clock pairs. 36-position connector (Samtec VHDCR-36-01-M-RA) ■ Software mates with industry-standard VHDCI cable assemblies. For more information, see www.acromag.com. SFP host connector (optional) ■ Engineering Design Kit SFP transceiver signals route directly to Virtex-6 FPGA. XMC-6VLX-EDK Provides user with basic information required to 2.5Gb/S maximum data rate. Engineering Design Kit (one kit required) develop a custom FPGA program. Kit must be ordered SFP copper (Gigabit Ethernet) or fibre optic modules PMCSW-API-VXW with the first purchase of a XMC-6VLX module (see ® available from Acromag. VxWorks software support package www.acromag.com for more information). PCISW-API-WIN ■ Environmental ® Windows DLL software support package Operating temperature ■ XMC Compliance PCISW-API-LNX Standard models: 0 to 70°C. ™ Linux support (website download only) Complies with ANSI/VITA 42.0 specification for XMC Storage temperature module mechanicals and connectors. -55 to 125°C. Complies with ANSI/VITA 42.3 specification for XMC Relative humidity modules with PCI Express interface. 5 to 95% non-condensing. Electrical/Mechanical Interface: Single-Width Module. Power 3.3V (±5%): Application dependent. 12V (±5%): Application dependent. MTBF Contact the factory. ■ ■ ■ ■ Tel 248-295-0310 Fax 248-624-9234 solutions@acromag.com www.acromag.com 30765 Wixom Rd, Wixom, MI 48393 USA All trademarks are property of their respective owners. Copyright © Acromag, Inc. 2016. Data subject to change without notice. Printed in USA 4/2016.