ACROMAG AXM-EDK
Description
AXM-EDK: Extension module design tool
The AXM-EDK board provides the standard Xilinx JTAG header as well as direct connections to the Xilinx FPGA. These general purpose LVTTL (Low Voltage TTL) I/O points allow the user to emulate AXM-D0x modules while using Xilinx's ChipScope® software tools. The AXM-EDK extension I/O module attaches to the PMC base board with a high-speed 150-pin header. The connector provides power to the extension board and multiple logic connections to the base board. Watch: FPGA Computing for Speed and Flexibility
Part Number
AXM-EDK
Price
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Manufacturer
ACROMAG
Lead Time
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Category
XMC Products » XMC FPGA Boards
Specifications
Key Features & Benefits
JTAG header can be used to directly program the FPGA or to interface with the FPGA debug software ChipScope
30 general-purpose front I/O pin connections can emulate differential channels using LVTTL signaling
16 auxiliary pins routed to two 8-pin SIP patters allow for full end-user customization
8 channels can be configured to generate interrupts for change-of-state (COS) and input level (polarity) match conditions
Categorization Information
Embedded I/O & Processors
XMC Products
XMC FPGA Boards
I/O Extension Modules
Datasheet
AXM-A30%20PMC%20Analog%20Input%20Extension%20Modules.pdf
58 KiB
Extracted Text
PMC Modules PMC Modules Block Diagram PCI Bus Connector 16MB FPGA Flash Memory Configuration CPLD 6 8 P Configurable I/O Transceivers i FPGA n PCI Bus • TTL I/O Interface Virtex II C • Differential (RS-422) I/O Controller o n 500K or 2M • TTL/Differential combo PLX9056 n System Gates e • LVDS I/O c t o r DC-to-DC 256K x 36 Power Supply RAM Memory Engineering Design Kit This kit provides you with the basic information required to develop a custom FPGA program for down- load to the Xilinx FPGA. Utilities help you load VHDL into the FPGA, and to establish DMA transfers between the FPGA and the CPU. It is also recommended that users should be familiar with Xilinx development tools. Acromag’s Engineering Design Kit includes: n Parts list and location n Schematics n Compiled FPGA file n Example VHDL code provided as selectable blocks of code Local Bus – example interface between PLX PCI9056 and FPGA SRAM – example code for read and write transfers to SRAM Interrupts – examples of change-of-state monitoring and interrupts to the PCI bus Field I/O – examples of direction control and I/O read/write capability Pin definitions – configuration file containing definition of all user I/O pins communicating with the FPGA Acromag, Inc. • PO Box 437, Wixom, MI 48393 • Phone: 248-295-0310 • Fax: 248-624-9234 • solutions@acromag.com • www.acromag.com 8400- 430d Printed in USA 1/07 Copyright © 2006 Acromag, Inc. Data subject to change without notice All trademarks are the property of their respective owners. PMC Modules
Frequently asked questions
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